1. Field of the Invention
The present invention generally relates to a semiconductor device, and especially relates to a semiconductor device including a metal thin-film resistor that consists of a metal thin film formed on an insulating film.
2. Description of the Related Art
In an analog integrated circuit, a great number of resistors are used as important elements. In recent years, a resistor (a metal thin film resistor) that consists of a metal thin film has attracted attention for its low temperature dependency of the resistance (called TCR). As a material of the metal thin film resistor, chromium silicon (CrSi), nickel chromium (NiCr), tantalum nitride (TaN), chromium silicide (CrSi2), chromium silicide nitride (CrSiN), chromium silicon oxy (CrSiO), and the like are used.
In a semiconductor device equipped with a metal thin film resistor, in order to attain a high degree of integration, the metal thin film resistor, the thickness of which is less than 1000 Å (Angstroms), is often used while aiming at a higher sheet resistance.
Conventional methods of making an electrical connection to the metal thin film resistor are as follows:
1) connecting a metal wire directly to the metal thin film resistor (for example, Patent Reference 1);
2) connecting a metal wire through a connection hole that is formed to an interlayer insulating film that is formed after forming a metal thin film resistor (for example, Patent Reference 2 and Patent Reference 3); and
3) connecting a metal wire to a barrier film that is formed on a metal thin film resistor layer (for example, Patent Reference 4 and Patent Reference 5).
The conventional methods 1), 2), and 3) above are specifically described.
The conventional method 1) is described with reference to FIGS. 25A-25F.
(1) A BPSG (borophospho silicate glass) film, which serves as a first interlayer insulating film 5 of a gate electrode of a transistor and a metal wiring, is formed on a wafer-shaped silicon substrate 1, on which a device separating oxide film 3, a transistor element, etc. (illustration is omitted) are formed, and a reflow process, e.g., is carried out (refer to FIG. 25A).
(2) A metal thin film 73 for forming a metal thin film resistor is formed all over the top of the silicon substrate 1 in about 20-500 Å thickness (refer to FIG. 25B).
(3) A resist pattern 75 for demarcating a region for forming the metal thin film resistor is formed on the metal thin film 73, the metal thin film 73 is patterned using the resist pattern 75 as a mask, and a metal thin film resistor 77 is formed (refer to FIG. 25C).
(4) The resist pattern 75 is removed, and a metal film 79 for wiring that consists of an AlSiCu film is formed all over the top of the first interlayer insulating film 5 including the top of the metal thin film resistor 77. A resist pattern 81 is formed on the metal film 79 for wiring such that the metal film 79 for wiring remains on both ends of the metal thin film resistor 77 by patterning using the resist pattern 81 (refer to FIG. 25D).
(5) A metal wiring pattern 83 is formed by patterning the metal film 79 for wiring using wet etching technology, the resist pattern 81 serving as a mask (refer to FIG. 25E). Generally, in manufacturing processes of common semiconductor devices, dry etching technology is used for forming the metal film 79 for wiring; however, since the metal thin film resistor 77 is etched by excessive etching, dry etching technology cannot be used in this case wherein the metal thin film resistor 77 with a small thickness is present directly under the metal film 79 for wiring. Therefore, it is necessary to carry out patterning of the metal film 79 for wiring by the wet etching technology.
(6) By removing the resist pattern 81, formation of the metal thin film resistor 77, and the metal wiring pattern 83 electrically connecting to the metal thin film resistor 77 is completed (refer to FIG. 25F).
Next, the conventional method 2) is described with reference to FIGS. 26A-26F.
(1) The device separating oxide film 3, the first interlayer insulating film 5, and the metal thin film resistor 77 are formed on the silicon substrate 1 in the same processes (1) through (3) as described above with reference to FIGS. 25A-25F (refer to FIG. 26A).
(2) Then, a CVD (chemical vapor deposition) oxide film 85, which serves as an interlayer insulating film of metal wiring, is formed on the first interlayer insulating film 5 including the top of the metal thin film resistor 77 at about a film thickness of 2000 Å (refer to FIG. 26B).
(3) A resist pattern 87 is formed on the CVD oxide film 85, which resist pattern is for forming connection holes 89 corresponding to both ends of the metal thin film resistor 77 for metal wiring connection. The connection holes 89 are formed by selectively removing the CVD oxide film 85 by wet etching technology using the resist pattern 87 as a mask (refer to FIG. 26C). Generally, in manufacturing processes of common semiconductor devices, dry etching technology is used when forming the connecting holes 89; however, in this case where the metal thin film resistor 77 is thinner than 1000 Å, it is difficult to prevent the connecting holes 89 from running through the metal thin film resistor 77. Accordingly, it is necessary to form the connecting holes 89 by the wet etching technology.
(4) A metal film 91 for wiring, consisting of an AlSiCu film, is formed on the CVD oxide film 85 including the inside of the connecting holes 89 (refer to FIG. 26D).
(5) A resist pattern 93 is formed on the metal film 91 for wiring for carrying out patterning so that the metal film 91 remains on both ends of the metal thin film resistor 77 for wiring (refer to FIG. 26E).
(6) A metal wiring pattern 95 is formed by patterning of the metal film 91 for wiring by dry etching technology using the resist pattern 93 serving as a mask. Since the CVD oxide film 85 is formed at the bottom of the metal film 91 for wiring at this time, even if the dry etching technology is used, the metal thin film resistor 77 is not etched.
By removing the resist pattern 93, formation of the metal thin film resistor 77, and the metal wiring pattern 95 for electrically connecting the metal thin film resistor 77 is completed (refer to FIG. 26F).
The conventional method 3) is described with reference to FIGS. 27A-27E.
(1) The device separating oxide film 3, the first interlayer insulating film 5, and the metal thin film resistor 77 are formed on the silicon substrate 1 by the same processes (1) through (3) described with reference to FIGS. 25A-25C (refer to FIG. 27A).
(2) A high melting point metal film 97, made of such as TiW, serving as a barrier film to metal wiring is formed on the first interlayer insulating film 5 including the top of the metal thin film resistor 77. Further, a metal film 99 for wiring, made of such as an AlSi film and an AlSiCu film is formed on the high melting point metal film 97 (refer to FIG. 27B).
(3) A resist pattern 101 for patterning the metal film 99 for wiring to remain on both ends of the metal thin film resistor 77 is formed on the metal film 99 for wiring (refer to FIG. 27C).
(4) A metal wiring pattern 103 is formed by patterning the metal film 99 for wiring by dry etching technology using the resist pattern 101 as a mask (refer to FIG. 27D). Since the high melting point metal film 97 is formed at the bottom of the metal film 99 for wiring at this time, even if dry etching technology is used, the metal thin film resistor 77 is not etched.
(5) The resist pattern 101 is removed. Then, a high melting point metal film pattern 105 is formed by selectively removing the high melting point metal film 97 by wet etching technology using the metal wiring pattern 103 as a mask. In this manner, the metal thin film resistor 77, the metal wiring pattern 103 for electrical connection of the metal thin film resistor 77, and the high melting point metal film pattern 105 are formed (refer to FIG. 27E). Here, since the high melting point metal film 97 is located immediately above the metal thin film resistor 77, patterning of the high melting point metal film 97 by dry etching technology is difficult.
Further, a semiconductor integrated circuit device equipped with a resistor that is formed on a top layer wiring electrode through an insulating film, and is connected with the top layer wiring electrode has been disclosed (for example, Patent Reference 6), although the resistor is not a metal thin film resistor. A manufacturing method of a semiconductor device applying such structure to a metal thin film resistor is described with reference to FIGS. 28A-28D.
(1) On the wafer-shaped silicon substrate 1, on which the device separating oxide film 3, a transistor element, etc. (illustration is omitted) are formed, the BPSG film serving as the first interlayer insulating film 5 of the gate electrode of the transistor and metal wiring is formed. After a reflow process, and the like, a metal wiring pattern 107 and a second interlayer insulating film 109 are formed on the first interlayer insulating film 5 (refer to FIG. 28A). The second interlayer insulating film includes a CVD oxide film, an SOG (spin on glass) film, and a CVD oxide film, that are layered in this sequence from bottom to top. FIGS. 28A-28D show the CVD oxide film, the SOG film, and the CVD oxide film constituting the second interlayer insulating film 109 in one body.
(2) A resist pattern 111 for demarcating a region to form a connecting hole 113 to the second interlayer insulating film 109 is formed (refer to FIG. 28B).
(3) The connecting hole 113 is formed to the second interlayer insulating film 109 on the wiring pattern 107 by selectively removing the second interlayer insulating film 109 by dry etching technology using the resist pattern 111 as a mask. At this time, the upper surface of the wiring pattern 107 is also removed by over-etching (refer to FIG. 28C).
(4) The resist pattern 111 is removed. Then, a metal thin film 115 for forming a metal thin film resistor all over the second interlayer insulating film 109 including the formation region of the connecting hole 113 is formed in a film thickness of about 20-500 Å (refer to FIG. 28D)
Then, the metal thin film 115 is patterned to a predetermined form, and the metal thin film resistor is formed.
[Patent reference 1] JPA, 2002-124639
[Patent reference 2] JPA, 2002-261237
[Patent reference 3] Japanese Patent No. 2699559
[Patent reference 4] Japanese Patent No. 2932940
[Patent reference 5] Japanese Patent No. 3185677
[Patent reference 6] JPA, 58-148443